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2490f?avr?12/03 features high-performance, low-power avr ? 8-bit microcontroller advanced risc architecture ? 130 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers + peripheral control registers ? fully static operation ? up to 16 mips throughput at 16 mhz ? on-chip 2-cycle multiplier non-volatile program and data memories ? 64k bytes of in-system reprogrammable flash endurance: 10,000 write/erase cycles ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-write operation ? 2k bytes eeprom endurance: 100,000 write/erase cycles ? 4k bytes internal sram ? up to 64k bytes optional external memory space ? programming lock for software security ? spi interface for in-system programming jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities according to the jtag standard ? extensive on-chip debug support ? programming of flash, eeprom, fuses, and lock bits through the jtag interface peripheral features ? two 8-bit timer/counters with separate prescalers and compare modes ? two expanded 16-bit timer/counters with separate prescaler, compare mode, and capture mode ? real time counter with separate oscillator ? two 8-bit pwm channels ? 6 pwm channels with programmable resolution from 1 to 16 bits ? 8-channel, 10-bit adc 8 single-ended channels 7 differential channels 2 differential channels with programmable gain (1x, 10x, 200x) ? byte-oriented two-wire serial interface ? dual programmable serial usarts ? master/slave spi serial interface ? programmable watchdog timer with on-chip oscillator ? on-chip analog comparator special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated rc oscillator ? external and internal interrupt sources ? six sleep modes: idle, adc noise reduction, power-save, power-down, standby and extended standby ? software selectable clock frequency ? atmega103 compatibility mode selected by a fuse ? global pull-up disable i/o and packages ? 53 programmable i/o lines ? 64-lead tqfp and 64-pad mlf operating voltages ? 2.7 - 5.5v for ATMEGA64l ? 4.5 - 5.5v for ATMEGA64 speed grades ? 0 - 8 mhz for ATMEGA64l ? 0 - 16 mhz for ATMEGA64 8-bit microcontroller with 64k bytes in-system programmable flash ATMEGA64 ATMEGA64l preliminary
2 ATMEGA64(l) 2490f?avr?12/03 pin configuration figure 1. pinout ATMEGA64 disclaimer typical values contained in this data sheet are based on simulations and characteriza- tion of other avr microcontrollers manufactured on the same process technology. min and max values will be available after the device is characterized. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 pen rxd0/(pdi) pe0 (txd0/pdo) pe1 (xck0/ain0) pe2 (oc3a/ain1) pe3 (oc3b/int4) pe4 (oc3c/int5) pe5 (t3/int6) pe6 (ic3/int7) pe7 (ss) pb0 (sck) pb1 (mosi) pb2 (miso) pb3 (oc0) pb4 (oc1a) pb5 (oc1b) pb6 pa3 (ad3) pa4 (ad4) pa5 (ad5) pa6 (ad6) pa7 (ad7) pg2(ale) pc7 (a15) pc6 (a14) pc5 (a13) pc4 (a12) pc3 (a11) pc2 (a10 pc1 (a9) pc0 (a8) pg1(rd) pg0(wr) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (oc2/oc1c) pb7 tosc2/pg3 tosc1/pg4 reset vcc gnd xtal2 xtal1 (scl/int0) pd0 (sda/int1) pd1 (rxd1/int2) pd2 (txd1/int3) pd3 (ic1) pd4 (xck1) pd5 (t1) pd6 (t2) pd7 avcc gnd aref pf0 (adc0) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck) pf5 (adc5/tms) pf6 (adc6/tdo) pf7 (adc7/tdi) gnd vcc pa0 (ad0) pa1 (ad1) pa2 (ad2) tqfp/mlf
3 ATMEGA64(l) 2490f?avr?12/03 overview the ATMEGA64 is a low-power cmos 8-bit microcontroller bas ed on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the atm ega64 achieves throughputs approaching 1 mips per mhz, allowing the system designer to optimize power consumption versus processing speed. block diagram figure 2. block diagram the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. program counter internal oscillator watchdog timer stack pointer program flash mcu control register sram general purpose registers instruction register timer/ counters instruction decoder data dir. reg. portb data dir. reg. porte data dir. reg. porta data dir. reg. portd data register portb data register porte data register porta data register portd timing and control oscillator oscillator interrupt unit eeprom spi usart0 status register z y x alu portb drivers porte drivers porta drivers portf drivers portd drivers portc drivers pb0 - pb7 pe0 - pe7 pa0 - pa7 pf0 - pf7 reset vcc agnd gnd aref xtal1 xtal2 control lines + - analog comp ara tor pc0 - pc7 8-bit data bus avcc usart1 calib. osc data dir. reg. portc data register portc on-chip debug jtag tap programming logic pen boundary- scan data dir. reg. portf data register portf adc pd0 - pd7 data dir. reg. portg data reg. portg portg drivers pg0 - pg4 2-wire serial interface
4 ATMEGA64(l) 2490f?avr?12/03 the ATMEGA64 provides the following features: 64k bytes of in-system programmable flash with read-while-write capabilities, 2k bytes eeprom, 4k bytes sram, 53 gen- eral purpose i/o lines, 32 general purpose working registers, real time counter (rtc), four flexible timer/counters with compare modes and pwm, two usarts, a byte ori- ented two-wire serial interface, an 8-channel, 10-bit adc with optional differential input stage with programmable gain, programmable watchdog timer with internal oscillator, an spi serial port, ieee std. 1149.1 compliant jtag test interface, also used for accessing the on-chip debug system and programming, and six software selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi port, and interrupt syst em to continue functioning. the power- down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. in power-save mode, the asyn- chronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o modules except asynchronous timer and adc, to minimize switching noise during adc conversions. in standby mode, the crystal/ resonator oscillator is running while the rest of the device is sleeping. this allows very fast start-up combined with low power consumption. in extended standby mode, both the main oscillator and the asynchro- nous timer continue to run. the device is manufactured using atmel?s high-density non-volatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the application flash memory. soft- ware in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel ATMEGA64 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. the ATMEGA64 avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in-cir- cuit emulators, and evaluation kits. atmega103 and ATMEGA64 compatibility the ATMEGA64 is a highly complex microcontroller where the number of i/o locations supersedes the 64 i/o location reserved in the avr instruction set. to ensure backward compatibility with the atmega103, all i/o locations present in atmega103 have the same location in ATMEGA64. most additional i/o locations are added in an extended i/o space starting from 0x60 to 0xff (i.e., in the atmega103 internal ram space). these location can be reached by using ld/lds/ldd and st/sts/std instructions only, not by using in and out instructions. the relocation of the internal ram space may still be a problem for atmega103 users. also, the increased number of interrupt vectors might be a problem if the code uses absolute addresses. to solve these problems, an atmega103 compatibility mode can be selected by programming the fuse m103c. in this mode, none of the functions in the extended i/o space are in use, so the internal ram is located as in atmega103. also, the extended interrupt vectors are removed. the ATMEGA64 is 100% pin compatible with atmega103, and can replace the atmega103 on current printed circuit boards. the application note ?replacing atmega103 by ATMEGA64? describes what t he user should be aware of replacing the atmega103 by an ATMEGA64.
5 ATMEGA64(l) 2490f?avr?12/03 atmega103 compatibility mode by programming the m103c fuse, the ATMEGA64 will be compatible with the atmega103 regards to ram, i/o pins and interrupt vectors as described above. how- ever, some new features in ATMEGA64 are not available in this compatibility mode, these features are listed below: one usart instead of two, asynchronous mode only. only the eight least significant bits of the baud rate register is available. one 16 bits timer/counter with two compare registers instead of two 16 bits timer/counters with three compare registers. two-wire serial interface is not supported. port g serves alternate functions only (not a general i/o port). port f serves as digital input only in addition to analog input to the adc. boot loader capabilities is not supported. it is not possible to adjust the frequency of the internal calibrated rc oscillator. the external memory interface can not release any address pins for general i/o, neither configure different wait states to different external memory address sections. only extrf and porf exist in the mcucsr register. no timed sequence is required for watchdog timeout change. only low-level external interrupts can be used on four of the eight external interrupt sources. port c is output only. usart has no fifo buffer, so data overrun comes earlier. the user must have set unused i/o bits to 0 in atmega103 programs. pin descriptions vcc digital supply voltage. gnd ground. port a (pa7..pa0) port a is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port a pins that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the ATMEGA64 as listed on page 71. port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pins that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the ATMEGA64 as listed on page 72.
6 ATMEGA64(l) 2490f?avr?12/03 port c (pc7..pc0) port c is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port c output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port c pins that are externally pulled low will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port c also serves the functions of special features of the ATMEGA64 as listed on page 75. in atmega103 compatibility mode, port c is output only, and the port c pins are not tri-stated when a reset condition becomes active. port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port d pins that are externally pulled low will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special features of the ATMEGA64 as listed on page 76. port e (pe7..pe0) port e is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port e output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port e pins that are externally pulled low will source current if the pull-up resistors are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. port e also serves the functions of various special features of the ATMEGA64 as listed on page 79. port f (pf7..pf0) port f serves as the analog inputs to the a/d converter. port f also serves as an 8-bit bi-directional i/o port, if the a/d converter is not used. port pins can provide internal pull-up resistors (selected for each bit). the port f output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port f pins that are externally pulled low will source current if the pull-up resistors are activated. the port f pins are tri-stated when a reset condition becomes active, even if the clock is not running. if the jtag interface is enabled, the pull-up resis- tors on pins pf7(tdi), pf5(tms) and pf4(tck) will be activated even if a reset occurs. the tdo pin is tri-stated unless tap states that shift out data are entered. port f also serves the functions of the jtag interface. in atmega103 compatibility mode, port f is an input port only. port g (pg4..pg0) port g is a 5-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port g output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port g pins that are externally pulled low will source current if the pull-up resistors are activated. the port g pins are tri-stated when a reset condition becomes active, even if the clock is not running. port g also serves the functions of various special features. in atmega103 compatibility mode, these pins only serves as strobes signals to the external memory as well as input to the 32 khz oscillator, and the pins are initialized to pg0 = 1, pg1 = 1, and pg2 = 0 asynchronously when a reset condition becomes active, even if the clock is not running. pg3 and pg4 are oscillator pins.
7 ATMEGA64(l) 2490f?avr?12/03 reset reset input. a low level on this pin for longer than the minimum pulse length will gener- ate a reset, even if the clock is not running. the minimum pulse length is given in table 19 on page 50. shorter pulses are not guaranteed to generate a reset. xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2 output from the inverting oscillator amplifier. avc c avcc is the supply voltage pin for port f and the a/d converter. it should be externally connected to v cc , even if the adc is not used. if the adc is used, it should be con- nected to v cc through a low-pass filter. aref aref is the analog reference pin for the a/d converter. pen this is a programming enable pin for the spi serial programming mode. by holding this pin low during a power-on reset, the device will enter the spi serial programming mode. pen has no function during normal operation.
8 ATMEGA64(l) 2490f?avr?12/03 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved ? ? ? ? ? ? ? ? .. reserved ? ? ? ? ? ? ? ? (0x9e) reserved ? ? ? ? ? ? ? ? (0x9d) ucsr1c ? umsel1 upm11 upm10 usbs1 ucsz11 ucsz10 ucpol1 189 (0x9c) udr1 usart1 i/o data register 186 (0x9b) ucsr1a rxc1 txc1 udre1 fe1 dor1 upe1 u2x1 mpcm1 187 (0x9a) ucsr1b rxcie1 txcie1 udrie1 rxen1 txen1 ucsz12 rxb81 txb81 188 (0x99) ubrr1l usart1 baud rate register low 191 (0x98) ubrr1h ? ? ? ? usart1 baud rate register high 191 (0x97) reserved ? ? ? ? ? ? ? ? (0x96) reserved ? ? ? ? ? ? ? ? (0x95) ucsr0c ? umsel0 upm01 upm00 usbs0 ucsz01 ucsz00 ucpol0 189 (0x94) reserved ? ? ? ? ? ? ? ? (0x93) reserved ? ? ? ? ? ? ? ? (0x92) reserved ? ? ? ? ? ? ? ? (0x91) reserved ? ? ? ? ? ? ? ? (0x90) ubrr0h ? ? ? ? usart0 baud rate register high 191 (0x8f) reserved ? ? ? ? ? ? ? ? (0x8e) adcsrb ? ? ? ? ? adts2 adts1 adts0 247 (0x8d) reserved ? ? ? ? ? ? ? ? (0x8c) tccr3c foc3a foc3b foc3c ? ? ? ? ?136 (0x8b) tccr3a com3a1 com3a0 com3b1 com3b0 com3c1 com3c0 wgm31 wgm30 131 (0x8a) tccr3b icnc3 ices3 ? wgm33 wgm32 cs32 cs31 cs30 134 (0x89) tcnt3h timer/counter3 ? counter register high byte 136 (0x88) tcnt3l timer/counter3 ? counter register low byte 136 (0x87) ocr3ah timer/counter3 ? output compare register a high byte 137 (0x86) ocr3al timer/counter3 ? output compare register a low byte 137 (0x85) ocr3bh timer/counter3 ? output compare register b high byte 137 (0x84) ocr3bl timer/counter3 ? output compare register b low byte 137 (0x83) ocr3ch timer/counter3 ? output compare register c high byte 137 (0x82) ocr3cl timer/counter3 ? output compare register c low byte 137 (0x81) icr3h timer/counter3 ? input capture register high byte 138 (0x80) icr3l timer/counter3 ? input capture register low byte 138 (0x7f) reserved ? ? ? ? ? ? ? ? (0x7e) reserved ? ? ? ? ? ? ? ? (0x7d) etimsk ? ? ticie3 ocie3a ocie3b toie3 ocie3c ocie1c 139 (0x7c) etifr ? ? icf3 ocf3a ocf3b tov3 ocf3c ocf1c 140 (0x7b) reserved ? ? ? ? ? ? ? ? (0x7a) tccr1c foc1a foc1b foc1c ? ? ? ? ?135 (0x79) ocr1ch timer/counter1 ? output compare register c high byte 137 (0x78) ocr1cl timer/counter1 ? output compare register c low byte 137 (0x77) reserved ? ? ? ? ? ? ? ? (0x76) reserved ? ? ? ? ? ? ? ? (0x75) reserved ? ? ? ? ? ? ? ? (0x74) twcr twint twea twsta twsto twwc twen ?twie 205 (0x73) twdr two-wire serial interface data register 207 (0x72) twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce 207 (0x71) twsr tws7 tws6 tws5 tws4 tws3 ? twps1 twps0 206 (0x70) twbr two-wire serial interface bit rate register 205 (0x6f) osccal oscillator calibration register 40 (0x6e) reserved ? ? ? ? ? ? ? ? (0x6d) xmcra ? srl2 srl1 srl0 srw01 srw00 srw11 30 (0x6c) xmcrb xmbk ? ? ? ? xmm2 xmm1 xmm0 32 (0x6b) reserved ? ? ? ? ? ? ? ? (0x6a) eicra isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 88 (0x69) reserved ? ? ? ? ? ? ? ? (0x68) spmcsr spmie rwwsb ? rwwsre blbset pgwrt pgers spmen 281 (0x67) reserved ? ? ? ? ? ? ? ? (0x66) reserved ? ? ? ? ? ? ? ? (0x65) portg ? ? ? portg4 portg3 portg2 portg1 portg0 87 (0x64) ddrg ? ? ? ddg4 ddg3 ddg2 ddg1 ddg0 87 (0x63) ping ? ? ? ping4 ping3 ping2 ping1 ping0 87 (0x62) portf portf7 portf6 portf5 portf4 portf3 portf2 portf1 portf0 86 (0x61) ddrf ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 87
9 ATMEGA64(l) 2490f?avr?12/03 (0x60) reserved ? ? ? ? ? ? ? ? 0x3f (0x5f) sreg i t h s v n z c 10 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 12 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 12 0x3c (0x5c) xdiv xdiven xdiv6 xdiv5 xdiv4 xdiv3 xdiv2 xdiv1 xdiv0 43 0x3b (0x5b) reserved ? ? ? ? ? ? ? ? 0x3a (0x5a) eicrb isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 89 0x39 (0x59) eimsk int7 int6 int5 int4 int3 int2 int1 int0 90 0x38 (0x58) eifr intf7 intf6 intf5 intf4 intf3 intf intf1 intf0 90 0x37 (0x57) timsk ocie2 toie2 ticie1 ocie1a ocie1b toie1 ocie0 toie0 107, 138, 158 0x36 (0x56) tifr ocf2 tov2 icf1 ocf1a ocf1b tov1 ocf0 tov0 107, 140, 158 0x35 (0x55) mcucr sre srw10 se sm1 sm0 sm2 ivsel ivce 30, 44, 62 0x34 (0x54) mcucsr jtd ? ? jtrf wdrfborfextrf porf 53, 256 0x33 (0x53) tccr0 foc0 wgm00 com01 com00 wgm01 cs02 cs01 cs00 102 0x32 (0x52) tcnt0 timer/counter0 (8 bit) 104 0x31 (0x51) ocr0 timer/counter0 output compare register 104 0x30 (0x50) assr ? ? ? ? as0 tcn0ub ocr0ub tcr0ub 105 0x2f (0x4f) tccr1a com1a1 com1a0 com1b1 com1b0 com1c1 com1c0 wgm11 wgm10 131 0x2e (0x4e) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 134 0x2d (0x4d) tcnt1h timer/counter1 ? counter register high byte 136 0x2c (0x4c) tcnt1l timer/counter1 ? counter register low byte 136 0x2b (0x4b) ocr1ah timer/counter1 ? output compare register a high byte 137 0x2a (0x4a) ocr1al timer/counter1 ? output compare register a low byte 137 0x29 (0x49) ocr1bh timer/counter1 ? output compare register b high byte 137 0x28 (0x48) ocr1bl timer/counter1 ? output compare register b low byte 137 0x27 (0x47) icr1h timer/counter1 ? input capture register high byte 138 0x26 (0x46) icr1l timer/counter1 ? input capture register low byte 138 0x25 (0x45) tccr2 foc2 wgm20 com21 com20 wgm21 cs22 cs21 cs20 155 0x24 (0x44) tcnt2 timer/counter2 (8 bit) 157 0x23 (0x43) ocr2 timer/counter2 output compare register 158 0x22 (0x42) ocdr idrd/ ocdr7 ocdr6 ocdr5 ocdr4 ocdr3 ocdr2 ocdr1 ocdr0 253 0x21 (0x41) wdtcr ? ? ? wdce wde wdp2 wdp1 wdp0 55 0x20 (0x40) sfior tsm ? ? ? acme pud psr0 psr321 70, 109, 143, 227 0x1f (0x3f) eearh ? ? ? ? ? eeprom address register high byte 20 0x1e (0x3e) eearl eeprom address register low byte 20 0x1d (0x3d) eedr eeprom data register 20 0x1c (0x3c) eecr ? ? ? ? eerie eemwe eewe eere 20 0x1b (0x3b) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 85 0x1a (0x3a) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 85 0x19 (0x39) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 85 0x18 (0x38) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 85 0x17 (0x37) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 85 0x16 (0x36) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 85 0x15 (0x35) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 85 0x14 (0x34) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 85 0x13 (0x33) pinc pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 86 0x12 (0x32) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 86 0x11 (0x31) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 86 0x10 (0x30) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 86 0x0f (0x2f) spdr spi data register 167 0x0e (0x2e) spsr spif wcol ? ? ? ? ?spi2x 167 0x0d (0x2d) spcr spie spe dord mstr cpol cpha spr1 spr0 165 0x0c (0x2c) udr0 usart0 i/o data register 186 0x0b (0x2b) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 187 0x0a (0x2a) ucsr0b rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 188 0x09 (0x29) ubrr0l usart0 baud rate register low 191 0x08 (0x28) acsr acd acbg aco aci acie acic acis1 acis0 228 0x07 (0x27) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 243 0x06 (0x26) adcsra aden adsc adate adif adie adps2 adps1 adps0 245 0x05 (0x25) adch adc data register high byte 246 0x04 (0x24) adcl adc data register low byte 246 0x03 (0x23) porte porte7 porte6 porte5 porte4 porte3 porte2 porte1 porte0 86 0x02 (0x22) ddre dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 86 0x01 (0x21) pine pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 86 register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
10 ATMEGA64(l) 2490f?avr?12/03 notes: 1. for compatibility with future devices, reserved bits shou ld be written to zero if accessed. reserved i/o memory address es should never be written. 2. some of the status flags are cleared by writing a logical one to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instruction s work with registers 0x00 to 0x1f only. 0x00 (0x20) pinf pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 87 register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
11 ATMEGA64(l) 2490f?avr?12/03 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? kz,n,v1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc knone3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 call k direct subroutine call pc knone4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2
12 ATMEGA64(l) 2490f?avr?12/03 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1sreg(s)1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 instruction set summary (continued)
13 ATMEGA64(l) 2490f?avr?12/03 clh clear half carry flag in sreg h 0 h 1 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a instruction set summary (continued)
14 ATMEGA64(l) 2490f?avr?12/03 ordering information note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. speed (mhz) power supply ordering code package operation range 8 2.7 - 5.5 ATMEGA64l-8ac ATMEGA64l-8mc 64a 64m1 commercial (0 c to 70 c) ATMEGA64l-8ai ATMEGA64l-8mi 64a 64m1 industrial (-40 c to 85 c) 16 4.5 - 5.5 ATMEGA64-16ac ATMEGA64-16mc 64a 64m1 commercial (0 c to 70 c) ATMEGA64-16ai ATMEGA64-16mi 64a 64m1 industrial (-40 c to 85 c) package type 64a 64-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, micro lead frame package (mlf)
15 ATMEGA64(l) 2490f?avr?12/03 packaging information 64a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64a, 64-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 64a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation aeb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 note 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 note 2 b 0.30 0.45 c 0.09 0.20 l 0.45 0.75 e 0.80 typ
16 ATMEGA64(l) 2490f?avr?12/03 64m1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64m1 , 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm micro lead frame package (mlf) c 64m1 01/15/03 common dimensions (unit of measure = mm) symbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 b 0.23 0.25 0.28 d 9.00 bsc d2 5.20 5.40 5.60 e 9.00 bsc e2 5.20 5.40 5.60 e 0.50 bsc l 0.35 0.40 0.45 notes: 1. jedec standard mo-220, fig. 1, vmmd. top view side view bottom view d e marked pin# 1 id e2 d2 b e pin #1 corner l seating plane a1 c a 1 2 3 c 0.08
17 ATMEGA64(l) 2490f?avr?12/03 erratas the revision letter in this section refers to the revision of the ATMEGA64 device. ATMEGA64, all rev. there are no errata for this revision of ATMEGA64. however, a proposal for solving prob- lems regarding the jtag instruction idcode is presented below. idcode masks data from tdi input the public but optional jtag instruction idcode is not implemented correctly according to ieee1149.1; a logic one is scanned into the shift register instead of the tdi input while shifting the device id register. hence, captured data from the pre- ceding devices in the boundary scan chain are lost and replaced by all-ones, and data to succeeding devices are replaced by all-ones during update-dr. if ATMEGA64 is the only device in the scan chain, the problem is not visible. problem fix / workaround select the device id register of the ATMEGA64 (either by issuing the idcode instruction or by entering the test-logic-reset state of the tap controller) to read out the contents of its device id register and possibly data from succeeding devices of the scan chain. note that data to succeeding devices cannot be entered during this scan, but data to preceding devices can. issue the bypass instruction to the ATMEGA64 to select its bypass register while reading the device id regis- ters of preceding devices of the boundary scan chain. never read data from succeeding devices in the boundary scan chain or upload data to the succeeding devices while the device id register is selected for the ATMEGA64. note that the idcode instruction is the default instruction selected by the test-logic-reset state of the tap-controller. alternative problem fix / workaround if the device ids of all devices in the boundary scan chain must be captured simul- taneously (for instance if blind interrogation is used), the boundary scan chain can be connected in such way that the ATMEGA64 is the fist device in the chain. update- dr will still not work for the succeeding devices in the boundary scan chain as long as idcode is present in the jtag instruction register, but the device id registered cannot be uploaded in any case.
18 ATMEGA64(l) 2490f?avr?12/03 datasheet change log for ATMEGA64 please note that the referring page numbers in this section are referred to this docu- ment. the referring revision in this section are referring to the document revision. changes from rev. 2490e-09/03 to rev. 2490f-12/03 1. updated ?calibrated internal rc oscillator? on page 40. changes from rev. 2490d-02/03 to rev. 2490e-09/03 1. updated note in ?xtal divide control register ? xdiv? on page 43. 2. updated ?jtag interface and on-chip debug system? on page 48. 3. updated ?test access port ? tap? on page 248 regarding jtagen. 4. updated description for the jtd bit on page 258. 5. added a note regarding jtagen fuse to table 119 on page 292. 6. updated r pu values in ?dc characteristics? on page 326. 7. updated ?adc characteristics ? preliminary data? on page 333. 8. added a proposal for solving problems regarding the jtag instruction idcode in ?erratas? on page 17. changes from rev. 2490c-09/02 to rev. 2490d-02/03 1. added reference to table 125 on page 296 from both spi serial programming and self programming to inform about the flash page size. 2. added chip erase as a first step under ?programming the flash? on page 323 and ?programming the eeprom? on page 324. 3. corrected ocn waveforms in figure 52 on page 124. 4. various minor timer1 corrections. 5. improved the description in ?phase correct pwm mode? on page 99 and on page 152. 6. various minor twi corrections. 7. added note under "filling the temporary buffer (page loading)" about writ- ing to the eeprom during an spm page load. 8. removed adhsm completely. 9. added note about masking out unused bits when reading the program counter in ?stack pointer? on page 12. 10. added section ?eeprom write during power-down sleep mode? on page 23. 11. changed v hyst value to 120 in table 19 on page 50.
19 ATMEGA64(l) 2490f?avr?12/03 12. added information about conversion time for differential mode with auto triggering on page 234. 13. added t wd_fuse in table 129 on page 309. 14. updated ?packaging information? on page 15. changes from rev. 2490b-09/02 to rev. 2490c-09/02 1. changed the endurance on the flash to 10,000 write/erase cycles. changes from rev. 2490a-10/01 to rev. 2490b-09/02 1. added 64-pad mlf package and updated ?ordering information? on page 14. 2. added the section ?using all locations of external memory smaller than 64 kb? on page 33. 3. added the section ?default clock source? on page 36. 4. renamed spmcr to spmcsr in entire document. 5. added some preliminary test limits and characterization data removed some of the tbd's and corrected data in the following tables and pages: table 2 on page 22, table 7 on page 36, table 9 on page 38, table 10 on page 38, table 12 on page 39, table 14 on page 40, table 16 on page 41, table 19 on page 50, table 20 on page 54, table 22 on page 56, ?dc characteristics? on page 326, table 132 on page 328, table 135 on page 331, table 137 on page 334, and table 138 - table 145. 6. removed alternative algortihm for leaving jtag programming mode. see ?leaving programming mode? on page 322. 7. improved description on how to do a polarity check of the adc diff results in ?adc conversion result? on page 242. 8. updated programming figures: figure 138 on page 294 and figure 147 on page 307 are updated to also reflect that avcc must be connected during programming mode. figure 142 on page 303 added to illustrate how to program the fuses. 9. added a note regarding usage of the ?prog_pageload (0x6)? and ?prog_pageread (0x7)? instructions on page 314. 10. updated ?two-wire serial interface? on page 196. more details regarding use of the twi power-down operation and using the twi as master with low twbrr values are added into the data sheet. added the note at the end of the ?bit rate generator unit? on page 202. added the description at the end of ?address match unit? on page 203. 11. updated description of osccal calibration byte. in the data sheet, it was not explained how to take advantage of the calibration bytes for 2, 4, and 8 mhz oscillator selections. this is now added in the following sections:
20 ATMEGA64(l) 2490f?avr?12/03 improved description of ?oscillator calibration register ? osccal(1)? on page 40 and ?calibration byte? on page 293. 12. when using external clock there are some limitations regards to change of frequency. this is descried in ?external clock? on page 41 and table 132 on page 328. 13. added a sub section regarding ocd-system and power consumption in the section ?minimizing power consumption? on page 47. 14. corrected typo (wgm-bit setting) for: ? ?fast pwm mode? on page 97 (timer/counter0). ? ?phase correct pwm mode? on page 99 (timer/counter0). ? ?fast pwm mode? on page 150 (timer/counter2). ? ?phase correct pwm mode? on page 152 (timer/counter2). 15. corrected table 81 on page 190 (usart). 16. corrected table 103 on page 262 (boundary-scan)
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